使用Xilinx FPGA时遇到下面的这个问题
ERROR:Place:1115 - Unroutable Placement! A clock IOB / BUFIO clock component
pair have been found that are not placed at a routable clock IOB / BUFIO site
pair. The clock IOB component is placed at site . The BUFIO component is placed at site
. Each BUFIO site has a select set of IOBs that can drive it.
If these IOBs are not used, the connection is not routable You may want to
analyze why this problem exists and correct it. This placement is UNROUTABLE in PAR and therefore, this error condition should be fixed in your design.
You may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote
this message to a WARNING in order to generate an NCD file. This NCD file can
then be used in FPGA Editor to debug the problem. A list of all the COMP.PINS
used in this clock placement rule is listed below. These examples can be used
directly in the .ucf file to demote this ERROR to a WARNING.
< NET "sys_clk_i" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR提示已经指明了问题原因,时钟管脚分配错误,硬件工程师把时钟放到了FPGA的非时钟管脚。
ERROR提示也指明了解决方案
如果这些信号在实际应用中不一定非要使用全局网络,这时可在约束文件(.ucf)中加上如下约束:
< NET "sys_clk_i" CLOCK_DEDICATED_ROUTE = FALSE; >
这样做是强制ISE不分配全局时钟网络给AC97Clk,布线就能成功了。
普通IO不能直接作PLL的时钟输入,专用时钟管脚可以;
普通IO可以通过BUFG再连到PLL的时钟输入上,但要修改PLL的设置 input clk的选项中要选择"No Buffer";
具体内部布局分配可以通过 Xilinx的FPGA Editor来查看,
ZYNQ的时钟管理也和之前的片子略有不同,之后在另一篇介绍,相关文档
xilinx FPGA普通IO作PLL时钟输入_the timing-driven placement phase encountered an e-CSDN博客
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